Diode, pulse-gating circuits



Sept. 11, 1956 R. D. FoRREsT 2,762,936

DIODE, PULSE-EATING CIRCUITS Filed Dec. 20, 1952 Jamai /40 da Jam 24d-a 44a moon, PULSE-GATING CrRCUrTs Richard D. Forrest, Los Angeles, Calif., assignor, by mesne assignments, to Hughes Aircraft Company, a corporation of Delaware Application December 20, 1952, Serial No. 327,133

Claims. (Cl. 307-885) This inventio-n relates to diode, pulse-gating circuits and, more particularly, to improvements in diode, pulsegating circuits utilized for applying triggering pulses to flip-dop circuits in response to an applied voltage-state signal and a counting or timing pulse.

The present invention is an improvement over a conventional type of pulse-gating circuit shown in Fig. 1 of this application. A gating circuit of this conventional type is also shown, for example, in Fig. 6a of U. S. Patent 2,644,887 to A. E. Wolfe, Jr.

The pulse-gating circuit shown in Fig. 1 of this application is particularly useful where a plurality of flip-flops are to be triggered simultaneously in response to applied counting or timing pulses, the pulses being applied to each cf the flip-flops through a single, associated pulse-gating circuit. At least one voltage-state signal is utilized to control each of the pulse-gating circuits. In the case of a binary counter, for example, the voltage-state signals are derived from the states of conduction of certain of the dip-flops in the counter.

While the pulse-gating circuit shown in Fig. 1 of this application functions satisfactorily under normal operating conditions, there are certain operating conditions which may cause the pulse-gating circuit to produce a spurious trigger pulse, which, of course, is undesirable. Although these operating conditions may occur infrequently, the simplicity of the present invention makes it economically feasible to insure against such contingencies. This is particularly true where the pulse gating circuits are utilized in a digital computer.

The particular operating conditions which may cause a spurious pulse to pass through the conventional gating circuit shown in Fig. 1 of this application occur when a ilip-op providing one of the voltage-state signals is to be triggered by the same counting or timing pulse which is applied to the pulse-gating circuit, such that its voltagestate signal is changed from a high level to a low level. lf the dip-flop providing the voltage-state signal is slow in responding to the triggering pulse 0r if the triggering pulse is delayed in transmission to the flip-dop, the delayed change in the voltage-state signal causes the gating circuit of Fig. 1 to produce a second pulse which may` again trigger the iiip-ilop to be controlled. K

Another feature of the present invention is that the pulse-gating circuits defined thereby may be utilized toV provide combined and and orl logic, as well as the and logic provided by the pulse-gating circuits ofthe type sho-wn in Fig. 1. If voltage-state signals cr and b are applied to separate input terminals of the pulse-gating circuit, and a count pulse Cp is applied to a third input terminal, a pulse is applied to a ipflop to be controlled when either or both of signals a and b are high-level signals representing binary 1, and a count pulse is applied. The logic of this condition may be expressed as: (a+b)..Cp; where the plus (i) represents the logical or and the dot the logical and The gating circuit of the present invention may also provide the logic: a.b.Cp, if signal n.11. produced byY a tes Patent O 2,762,936 Patented Sept. 1l, 1956` lower-level and circuit is applied to one input terminal of the gating circuit and signal Cp applied to a second input terminal of the gating circuit.

The basic embodiment of the present invention comprises: a pulse-gating diode; a gating resistor having one end connected to the pulse-gating diode, and the other end connected to a reference-potential source; and n input diodes coupled in parallel to the junction of the gating resistor and the pulse-gating diode, the letter n being utilized to indicate that there may be any number of input diodes. A voltage-state signal is applied to each of the n input diodes; the output signal produced thereby being defined by the function (a+ rt).Cp, where the letters a through n are utilized to indicate voltage signals applied to input diodes a through n, reSDfctively.

Accordingly, it is an object of the present invention to provide a diode, a pulsefgating circuit, wherein no spurious trigger pulse is caused due to the delayed change of an applied voltage-state signal from a high level to a low level.

Another object is to provide a pulse-gating circuit, wherein and and or logic may be combined.

Still another object is to provide an improved diode, pulse-gating circuit for applying pulse signals to an input circuit of a dip-flop in response to the high-level state of a V2-level control signal.

The novel features which are believed to be characteristic of the invention, both as to its organization and the method of operation, together with further objects and advantages thereof, will be better understood from the following description considered in connection with the accompanying drawings in which two embodiments of the invention are illustrated yby way of examples. It is to be expressly understood, however, that the drawings are for the purpose of illustration and description only, and are not intended as a definition of the limits of the invention.

Fig. l is a schematic diagram of a conventional type of pulse-gating circuit for providing an and function;

Fig. 2 is a schematic diagram of a diode, pulse-gating circuit according to the present invention;

Fig. 3 lis a composite diagram of the wave :forms of signals which occur under certain operating conditions in the pulse-gating circuit shown in Fig. 1;

Fig. 4 is a composite diagram of the wave forms of signals which occur, under the same operating conditions as those illustrated in Fig. 3, in the pulse-gating circuit shown in Fig. 2; and

Fig. 5 is a schematic diagram of another form of diode, pulse-gating circuit according to the present invention.

In order to fully understand the operation of the pulsegating circuit provided by the present invention it is necessary to consider the operation of the pulse-gating circuit shown in Fig. 1 of this specication; the wave forms of signals appearing in the circuit of Fig. 1 during an illus. trative oper-ation being shown in Fig. 3. The operation ofthe circuit shown in Fig. 1 will be considered only to the extent necessary to point out the improvement provided by the present invention with respect to the possibility of spurious triggering signals being produced. Reference may be made to the patent to Wolfe -for further details with respect to the manner in which the circuit shown in Fig. 1 provides the desired and function.

Wave forms 320 and 340, shown in Fig. 3, illustrate the types of signals which may be produced by negative pulse source 12.9 and voltage-state, signal source 140, respectively. lt will be noted that wave forms 320 and 340 represent negative-going signals; signal 321) dropping rst from a high'level Eh to a low level El, and signal 34) falling from level Ehl to level El after a time interv-al designated as 'I. Although in most systems using voltage-state gating circuits, all hip-Hops are triggered simultaneously by counting or timing pulses, the delay T may be due to a pulse-transmission delay in passing a pulse signal through acable, or it may be due to the delayed reaction of a flip-flop producing the voltage-state signal.

Since diodes 111 .and 113 become front biased, respectively, when the signal produced by source 120 assumes a lower level than that produced by source 140, and vice-versa; it is apparent that signal 314, appearing at junction 114, in Fig. l, assumes a waveshape similar to the lower-level portion of each of signals 320 and 340. Since signal 32@ falls iirst from level Eh to El, signal 314 is first similar to signal 320, as diode 111 becomes front biased and diode 113 becomes back biased. In a similar manner, as soon as the level of signal 320 rises above that of 340, signal 314 assumes substantially the waveshape of signal 340, as diode 113 becomes front biased and diode 111 becomes back biased.

As the potential at junction 114 varies according to signal 314, capacitor 115 discharges from its original voltage level Eh to the new level El, through load resistor 132 and either of sources 120 or 140, depending upon which is producing the lower-level signal. Since each of sources 129 and 149 is a low-impedance source, the discharge time for capacitor 115 is dependent substantially upon its capacitance and the resistance of load resistor 132.

Except for the peculiar waveshape of the signal appearing at junction 114, then, the signal appearing across load resistor 132 would be an exponential discharge signal. However, at the beginning of the discharge period of capacitor 115, the voltage across load resistor 132 increases more rapidly than a normal exponential discharge voltage, due to the increasing voltage appearing at junction 114. When the voltage-state signal produced by source 140 drops to level El, the signal appearing across load resistor 132, makes a second, negative-going change and then returns to the normal exponential discharge wave form. The second negative-going change is that portion which has been referred to as the spurious signal and may be sufciently negative to fall below the triggering level of the flip-flop to be controlled. This level is designated as Et in Figures 3 and 4. The tirst negative-going portion of signal 336, it will be noted, is the desired triggering pulse which indicates that the and function has a value of l.

One embodiment of a pulse-gating circuit according to the present invention for providing an operation similar to that described above, is shown in Fig. 2, where it may be seen that pulses produced by a negative pulse source 220 are applied by pulse-gating circuit 210 to a nip-flop input circuit 23% in response to voltage-state signal sources 240-a, and 2411-71.

As shown in Fig. 2, pulsegating circuit 210 comprises: an input diode 211 having its cathode coupled to the output terminal of negative pulse source 220; a gating resistor 212 having one end connected to the anode of diode 211 at a junction 214, and the other end connected to ground; n input diodes Z13-a through Z13-n having their anodes connected to voltage-state signal sources 240-a through 240-n, respectively, and having their cathodes coupled in parallel to the junction 214 of diode 211 and gating resistor 212; and a capacitor 215 coupling junction 214 to input circuit 230.

Input circuit 23@ includes a load resistor 232 having one end connected to capacitor 215 at a junction 236 and the other end connected to ground, and a diode 234, having its cathode connected to the junction 236 of load resistor 232 and capacitor 215, and its anode coupled to the flip-flop which is to be controlled.

Consider now the operation of the circuit shown in Fig. 2 under the operating conditions considered above, reference being made also to Fig. 4. Wave forms 420 and 440 shown in Fig. 4 correspond to wave forms ,3211 ,and

340 of Fig. 3, and are produced by signal sources 220 and 240-a, respectively. In the particular operation considered, it is assumed that the circuit shown in Fig. 2 includes only one voltage-state signal source 24o-a. It will be noted that wave forms 414 and 436 in Fig. 4, corresponding to wave forms 314 and 336 of Fig. 3, respectively, do not include any sharply changing portions due to the change in level of the voltage-state signal source.

The reason for this is that diode Z13-a does not become front biased as signal 446 falls below signal 420; and consequently, the discharge path for capacitor 215 has a much greater time constant than the corresponding discharge path for capacitor in the circuit of Fig. l. As a result, wave form 414 does not assume the waveshape of wave form 440, but rather has a gradual exponential decay after signal 440 assumes a lower level than signal 420.

Signal 436 appearing across load resistor 232, then, no longer includes the second sharp, negative-going portion. The positive-going portion causes no difficulty because diode 234 in input circuit 230 prevents a positive signal from affecting the flip-flop to be controlled.

From the operation thus considered, it may be seen then that the present invention eliminates spurious triggering signals under the same operating conditions as those described above for the pulse-gating circuit of Fig. l.

Consider now the operation of the circuit shown in Fig. 2 in providing the combined and and or" function(a|...|-...+...-ln).Cp.

When any one of the voltage-state signals produced by sources 241i through 24o-n are high-level signals, the corresponding input diode is front biased and a high-level signal appears at junction 214. Capacitor 215, then, charges to a voltage diierence equal to Eh, where Eh again is the higher of the two levels of the voltage-state signals. When a count or timing pulse is produced by negative pulse source 220, then, diode 211 is front biased and signal 414 at junction 214 has a waveshape substantially the same as that of signal 420. The signal appearing across load resistor 232, as capacitor 215 discharges, may be similar to signal 414 shown in Fig. 4, if one of the voltage-state signals returns suddenly to level Eh, or it may be substantially a reproduction of the signal produced by source 220, if none of the voltage-state signal levels change. Thus, the high-level state of any one of signals 240-a through 240-n is the or condition desired,

and the application of the count pulse or time pulse isY the and condition.

While the voltage-state signals may be derived directly from dip-flops, it is desirable to include an isolation network to prevent negative pulses produced by source 220 from being applied to the flip-nop input circuit. An isolation network which is suitable is illustrated in voltagestate signal source 24o-n. It will be noted that this network may also be considered an and circuit of a conventional type; and thus, it is possible to provide a function (a4-xy). Cp, where x and y are signals produced by source 24U-n.

Another way of providing isolation between source 220 and other flip-hops which may be in the system, is shown in Fig. 5. Referring now to Fig. 5, it will be noted that the circuit shown therein is substantially the same as that shown in Fig. 2 (similar elements being given the same reference numeral), except that an isolation network 550 is introduced between the parallel-coupled voltage-state signal sources and junction 214; and that gating resistor 212 is now connected to a positive potential, not shown. The potential applied to gating resistor 212 is somewhat greater than Eh. In an illustrative embodiment, where Eh and El are volts, and 125 volts, respectively, the potential applied to gating resistor 212 is 265 volts.

As shown in Fig. 5, the isolation network 550 includes a diode 551, having its anode connected to junction 214 anditsnethode connected to one end of an isolation resistor S52. The other end of isolation resistor 552 is connected to ground. The junction of diode 551 and resistor 552 is connected to cathodes of parallel-connected diodes Z13-rz through 213-11. The operation of the circuit shown in Fig. 5 is substantially the same of that of the circuit shown in Fig. 2, further consideration therefore being deemed unnecessary.

While the embodiments described herein have been limited to those responsive to negative, counting or timing pulses, it should be apparent to one skilled in the art that the positive pulses may be used as well, provided that suitable changes are made in the diode connections and applied potentials. In one manner of converting the circuit shown in Fig. 2 from a negative pulse system into a positive pulse system, all of the diodes are reversed and the ground connection made to gating resistor 212 is changed to a connection to a positive potential, such as that described above.

It is apparent from the foregoing description that the present invention provides a diode, pulse-gating circuit, wherein no spurious trigger pulse is caused due to the delayed change of an applied voltage-state signal from a high level to a low level; and wherein and and or logic may be combined. While only two species have been shown in detail, other modifications will be apparent to one skilled in the art.

What is claimed is:

l. In a computer system, wherein triggering pulses are selectively applied to a first flip-flop in response to one voltage level of a two-level control signal derived from the conduction state of a second flip-flop, the triggering pulses being also selectively applied to the second iiip-fiop, the combination comprising: a first diode having anode and cathode terminals; first means for applying the triggering pulses to one terminal of said first diode; second means for applying the control signal to the other terminal of said first diode, said second means including a second diode having anode and cathode terminals and coupling means for connecting the anode terminal of one of said diodes to the cathode terminal of the other of said diodes; and output means including a capacitor and a gating resistor having one end connected to said capacitor, the common junction of said resistor and capacitor being connected to said other terminal of said first diode, said output means producing an output pulse upon time coincidence between an applied triggering pulse and the one voltage level of the control signal.

2. A diode pulse-gating circuit for selectively passing applied negative pulses in response to one voltage level of a two-level electrical control signal, said pulse-gating circuit comprising: a first diode having anode and cathode terminals; tirst means for applying the negative pulses to the cathode terminal of said first diode; second means for applying the control signal to the anode terminal of said first diode, said second means including a second diode having anode and cathode terminals, an isolation resistor having one end connected to the cathode terminal of said second diode, and a third diode having a cathode terminal connected to said one end of said isolation resistor and an anode terminal connected to the anode terminal of said tirst diode, the control signal being applied to the anode terminal of said second diode so that said rst and second diodes are front biased when the level of au applied negative pulse is lower than the level of the control signal and back biased when the level of the control signal is lower than the level of an applied negative pulse; and output means, including a capacitor electrically connected to the anode terminal of said first diode, for producing an output pulse upon time coincidence between an applied negative pulse and the one voltage level of the control signal.

3. A gating circuit for selectively passing pulses of an applied pulse series in response to a predetermined voltage level of at least one of a plurality of applied twolevel control signals, said gating circuit comprising: a first diode having anode and cathode terminals; a plurality of second diodes, one for each of said control signals, each of said second diodes having an anode terminal and a cathode terminal; coupling means connecting one terminal of said first diode to the opposite terminal of each of said second diodes so as to form a circuit for passing current in only one direction through said first diode in series with a parallel configuration of said second diodes; first means for applying the pulse series to the other terminal of said first diode; second means for applying the plurality of control signals individually to the other terminals of said plurality of second diodes; and output means including a capacitor electrically connected to said one terminal of said first diode for producing an output pulse upon time coincidence of an applied pulse and the predetermined voltage level of at least one of said control signals.

4. The gating circuit claimed in claim 3 wherein said applied pulses are of negative polarity, said predetermined voltage level is the relatively high level, said one terminal of said first diode is the anode terminal, said opposite terminal of each of said second diodes is the cathode terminal, said other terminal of said first diode is the cathode terminal, and said other terminals of said plurality of second diodes are the anode terminals, whereby said plurality of second diodes provides an or circuit for said plurality of control signals, and said first diode together with said output means provides an and circuit for combining said applied pulses with the output signal from said or circuit.

5. A diode, pulse-gating circuit for selectively passing applied negative pulses in response to one voltage level of a two-level electrical control signal, said pulse-gating circuit comprising: a first diode having anode and cathode terminals; first means for applying the negative pulses to the cathode terminal of said first diode; a second diode having anode and cathode terminals; second means for applying the control signal to the anode terminal of said second diode; coupling means connected between the cathode of said second diode and the plate of said first diode so that said diodes are front biased when the level of an applied negative pulse is lower than the level of the control signal and back biased when the level of the control signal is lower than the level of an applied negative pulse, said coupling means including an isolating network; and output means including a capacitor electrically connected to the anode terminal of said first diode.

References Cited in the le of this patent UNITED STATES PATENTS 2,535,303 Lewis Dec. 26, 1950 2,570,716 Rochester Oct. 9, 1951 2,628,346 Burkhart Feb. 10, 1953 2,636,133 Hussey Apr. 21, 1953 2,644,887 Wolfe, Jr. July 7, 1953 2,644,897 Lo July 7, 1953 2,679,617 Mullaney et al May 25, 1954 2,685,039 Scarbrough et al July 27, 1954 OTHER REFERENCES Proceedings of I. R. E., May 1950, pp. 511 to 514, Diode Coincidence and Mixing Circuits in Digital Computers, by Tung Chang Chen. 

